| 17 | 17 | We currently investigate how to minimize the pipelining latency at the mapping and scheduling stages. Therefore, we examine new cost functions and evaluate their performance in different computing resource management scenarios. We, furthermore, address the scalability of the ''tw''-mapping with the objective of applying it to large processor arrays and multiprocessor systems-on-chip (MPSoCs). We work on extensions of the ''tw''-mapping algorithm itself, but, also, on pre and postprocessing add-ons. |
